Last Edit: 2009.03.01

This page is dedicated to my master thesis which is still on writing. To achieve a better quality, I decide to publish the thesis draft in my blog so that it is accessable to everyone. If you happen to read it, comments are welcome.

The thesis project implemented a open source general purpose embedded platform with OpenRISC OR1200 processor and based on Terasic's DE2-70 board.

Title: Open source embedded platform based on OpenRISC and DE2-70
Chapter 1. Introduction
Chapter 2. Open Cores in a Commercial Perspective (finished)
Chapter 3. Platform Overview
Chapter 4. OpenRISC OR1200 Processor
Chapter 5. WISHBONE Specification and Conmax IP Core (finished)
Chapter 6. Peripherals
Chapter 7. Software Development
Chapter 8. Porting uC/OS-II to the platform
Chapter 9. Porting uC/TCP-IP to the platform
Chapter 10. Conclusion
Appendix A. Thesis Announcement
Appendix B. A Step by step Instruction to Repeat the Thesis Project (finished)

Finished Chapters:

Chapter 2. Open Cores in a Commercial Perspective (Last revised: 2008/12/25)
- This chapter tries to answer whether it is good to use open cores for commercial purpose.
- Some open source licenses like BSD License, GPL and LGPL are introduced.

Chapter 5. WISHBONE Specification and Conmax IP Core (Last revised: 2009/01/21)
- Introduce the WISHBONE SoC interconnection standard.
- Cover the descriptions to all WISHBONE bus transactions, including the "registered
  feedback bus cycles", i.e. the burst transaction.
- Introduce the Conmax IP Core, which implements a WISHBONE interconnection with
  matrix structure.

Appendix B. A Step by step Instruction to Repeat the Thesis Project
(Last revised: 2009/03/01)
- This appendix tells how to repeat our thesis project with our Project Archive Zip file.

Key Words:
Open Core, BSD License, GPL, LGPL,
WISHBONE, Conmax,

Downloads:
Chapter 2. Open Cores in a Commercial Perspective (Last revised: 2008/12/25)
Chapter 5. WISHBONE Specification and Conmax IP Core (Last revised: 2009/01/21)
Appendix B. A Step-by-step Instruction to Repeat the Thesis Project
(Last revised: 2009/03/01)

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Dear List,

This is Xiang Li and Lin Zuo. We are master students of the SOC program of KTH, Sweden. Here we'd like to present our thesis to the community.

The thesis implements general purpose embedded platform which uses the OpenRISC OR1200 processor as the CPU. It is targeted to an ALTERA FPGA development board (Terasic's DE2-70). We made a demo program which is able to decode a small MP3 file in PC, download the music data to the board via an Ethernet connection, and finally play the music on the board. See features below for more details.

The thesis was proposed by and performed in a Swedish company ENEA (Malmö / Lund branch). It started at January 2008 and most of the design was done by the end of June 2008. So far, Lin has finished his thesis, while Xiang is still working on his thesis writing.

Here is the link to the download webpage:
http://www.olivercamel.com/post/master_thesis.html
At there, you can find the project zip file (about 65MB) as well as Xiang's thesis draft. Lin's thesis has already included in the zip file.

We don't know if it is possible to upload the project zip file to opencores.org's CVS as well, and maybe find a place under the OpenRISC’s webpage. If so, we would like to do that. Someone please direct us an instruction link which tells how to.

We would like to thank our supervisors Johan Jörgensen (ENEA) and Ingo Sander (KTH).

We hope that our work could contribute a little to open core community. Comments and feedbacks are welcome!

Best regards,
Xiang Li, Lin Zuo
2009/01/14

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  Thesis Project Features
===================================================

ORPXL (the Openrisc Reference Platform designed by Xiang and Lin)

  - General purpose embedded platform
  - Low cost because of using open cores and open source software
  - Most source code of the platform is available
    -- except for the ALTERA's built-in IPs like RAM, FIFO, PLL
    -- uC/OS-II and uC/TCP-IP are not open source, but their source code is provided
  - Based on Terasic's DE2-70 board, and ALTERA's FPGA Cyclone II

  - OpenRISC OR1200 Processor
    -- System running at 50MHz, no cache, no MMU
  - WISHBONE Interconnection Standard and CONMAX IP Core
  - Memory Controller IP Core
    -- 32KB On-chip memory
    -- 2MB SSRAM
    -- 64MB SDRAM
  - RS232 by UART16550 IP Core
  - Buttons, LEDs, 7-Segments by GPIO IP Core
  - WISHBONE Interface for WM8731 Audio CODEC (DAC only)
  - WISHBONE Interface for DM9000A Ethernet controller

  - Porting uC/OS-II to OpenRISC processor
  - Porting uC/TCP-IP to OpenRISC processor
    -- we can achieve about 3KB speed for a stable connection
  - LibMAD (running in PC) is used to conver MP3 to WAV format
  - bootloader that download software binary files via RS232
  - ihex2mif that conver ihex format to ALTERA's mif format

===================================================
  Project Downloads: orpXL_release_20081116.zip (about 65MB)
===================================================